Design and CAD methodologies for low power gate-level monolithic 3D ICs-Reference-Cited by-同舟云学术

Design and CAD methodologies for low power gate-level monolithic 3D ICs

Published:2014-08-11 Issue: Volume: Page:
ISSN:
Container-title:Proceedings of the 2014 international symposium on Low power electronics and design
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Author:

Panth Shreepad A.¹,Samadi Kambiz²,Du Yang²,Lim Sung Kyu¹

Affiliation:

1. Georgia Institute of Technology, Atlanta, USA

2. Qualcomm Research, San Diego, USA

Publisher

ACM

Link

Reference7 articles.

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