A flash-based digital circuit design flow-Reference-Cited by-同舟云学术

A flash-based digital circuit design flow

Published:2016-11-07 Issue: Volume: Page:
ISSN:
Container-title:Proceedings of the 35th International Conference on Computer-Aided Design
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Author:

Abusultan Monther¹,Khatri Sunil P.¹

Affiliation:

1. Texas A&M University

Publisher

ACM

Link

https://dl.acm.org/doi/pdf/10.1145/2966986.2966990

Reference25 articles.

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3. Novel Co-Design of NAND Flash Memory and NAND Flash Controller Circuits for Sub-30 nm Low-Power High-Speed Solid-State Drives (SSD)

4. S. L. et al. "A 128Gb 2b/cell NAND flash memory in 14nm technology with tPROG=640us and 800MB/s I/O rate " in 2016 IEEE International Solid-State Circuits Conference (ISSCC) pp. 138--139 Jan 2016. S. L. et al. "A 128Gb 2b/cell NAND flash memory in 14nm technology with tPROG=640us and 800MB/s I/O rate " in 2016 IEEE International Solid-State Circuits Conference (ISSCC) pp. 138--139 Jan 2016.

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