An Efficient Parallel Architecture for Convolutional Neural Networks Accelerator on FPGAs-Reference-Cited by-同舟云学术

An Efficient Parallel Architecture for Convolutional Neural Networks Accelerator on FPGAs

Published:2022-06-23 Issue: Volume: Page:
ISSN:
Container-title:2022 6th International Conference on High Performance Compilation, Computing and Communications (HP3C)
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Author:

Hongmin Huang¹,Xueming Li²,Yadong Qin²,Xianghong Hu³,Xiaoming Xiong⁴

Affiliation:

1. School of Automation, Guangdong University of Technology, China and Company of Chipeye Microelectronics Foshan Ltd., China

2. School of Automation, Guangdong University of Technology, China

3. School of Integrated Circuits, Guangdong University of Technology, China

4. School of Integrated Circuits, Guangdong University of Technology, China and Company of Chipeye Microelectronics Foshan Ltd., China

Funder

Key-Area Research and Development Program of Guangdong

Publisher

ACM

Link

https://dl.acm.org/doi/pdf/10.1145/3546000.3546010

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3. [ 3 ] Shahmustafa Mujawar , Divya Kiran , and Hariharan Ramasangu . An efficient cnn architecture for image classification on fpga accelerator . In 2018 Second International Conference on Advances in Electronics, Computers and Communications (ICAECC) , pages 1– 4 . IEEE, 2018. [3] Shahmustafa Mujawar, Divya Kiran, and Hariharan Ramasangu. An efficient cnn architecture for image classification on fpga accelerator. In 2018 Second International Conference on Advances in Electronics, Computers and Communications (ICAECC), pages 1–4. IEEE, 2018.

4. YOLO9000: Better, Faster, Stronger

5. A Full Featured Configurable Accelerator for Object Detection With YOLO

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