Power modeling on FPGA
Author:
Affiliation:
1. Univ Rennes, Rennes, France
Publisher
ACM
Link
https://dl.acm.org/doi/pdf/10.1145/3203217.3204462
Reference11 articles.
1. Power estimation for intellectual property-based digital systems at the architectural level
2. Architecture evaluation for power-efficient FPGAs
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4. High-Level Synthesis Hardware Design for FPGA-Based Accelerators: Models, Methodologies, and Frameworks;IEEE Access;2022
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