High-level power estimation techniques in embedded systems hardware: an overview
Author:
Publisher
Springer Science and Business Media LLC
Subject
Hardware and Architecture,Information Systems,Theoretical Computer Science,Software
Link
https://link.springer.com/content/pdf/10.1007/s11227-022-04798-5.pdf
Reference43 articles.
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3. Ananthanarayana T, Lopez S, Lukowiak M (2017) Power analysis of HLS-designed customized instruction set architectures. Proceedings - 2017 IEEE 31st International Parallel and Distributed Processing Symposium Workshops, IPDPSW 2017 pp. 207–212. https://doi.org/10.1109/IPDPSW.2017.59
4. Arpinen T, Salminen E, Hämäläinen TD, Hännikäinen M (2012) MARTE profile extension for modeling dynamic power management of embedded systems. J Syst Archit 58(5):209–219. https://doi.org/10.1016/j.sysarc.2011.01.003
5. Carballo PP, Espino O, Neris R, Hernández-Fernández P, Szydzik TM, Núñez A (2013) Scalable video coding deblocking filter FPGA and ASIC implementation using high-level synthesis methodology. Proceedings - 16th Euromicro Conference on Digital System Design, DSD 2013 pp. 415–422. https://doi.org/10.1109/DSD.2013.52
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