Maximizing Energy Efficiency in NTC by Variation-Aware Microprocessor Pipeline Optimization
Author:
Affiliation:
1. Chair of Dependable Nano Computing (CDNC), Karlsruhe Institute of Technology (KIT), Karlsruhe, Germany
Publisher
ACM
Link
https://dl.acm.org/doi/pdf/10.1145/2934583.2934635
Reference22 articles.
1. EnergySmart: Toward energy-efficient manycores for Near-Threshold Computing
2. Assessing the performance limits of parallelized near-threshold computing
3. Coping with Parametric Variation at Near-Threshold Voltages
4. Shapeshifter: Dynamically changing pipeline width and speed to address process variations
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1. Twenty Years of Near/Sub-Threshold Design Trends and Enablement;IEEE Transactions on Circuits and Systems II: Express Briefs;2021-01
2. Cross-Layer Reliability, Energy Efficiency, and Performance Optimization of Near-Threshold Data Paths;Journal of Low Power Electronics and Applications;2020-12-03
3. A Comprehensive Reliability Analysis Framework for NTC Caches: A System to Device Approach;IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems;2019-03
4. Fine-Grained Energy-Constrained Microprocessor Pipeline Design;IEEE Transactions on Very Large Scale Integration (VLSI) Systems;2018-03
5. Error Propagation Aware Timing Relaxation For Approximate Near Threshold Computing;Proceedings of the 54th Annual Design Automation Conference 2017;2017-06-18
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