Reducing Power Consumption of GPGPUs Through Instruction Reordering-Reference-Cited by-同舟云学术

Reducing Power Consumption of GPGPUs Through Instruction Reordering

Published:2016-08-08 Issue: Volume: Page:
ISSN:
Container-title:Proceedings of the 2016 International Symposium on Low Power Electronics and Design
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Author:

Aghilinasab Homa¹,Sadrosadati Mohammad¹,Samavatian Mohammad Hossein¹,Sarbazi-Azad Hamid²

Affiliation:

1. Department of Computer Engineering, Sharif University of Technology, Tehran, Iran

2. Department of Computer Engineering, Sharif University of Technology, Tehran, Iran and Computer Science School, Institute for Researches in Fundamental Sciences, Tehran, Iran

Publisher

ACM

Link

https://dl.acm.org/doi/pdf/10.1145/2934583.2934606

Reference23 articles.

1. Warped register file: A power efficient register file for GPGPUs

2. Warped gates

3. Analyzing CUDA workloads using a detailed GPU simulator

4. Rodinia: A benchmark suite for heterogeneous computing

5. MP3: Minimizing performance penalty for power-gating of Clos network-on-chip

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