Warped register file: A power efficient register file for GPGPUs-Reference-Cited by-同舟云学术

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Warped register file: A power efficient register file for GPGPUs

Published:2013-02 Issue: Volume: Page:
ISSN:
Container-title:2013 IEEE 19th International Symposium on High Performance Computer Architecture (HPCA)
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Author:

Abdel-Majeed M.,Annavaram M.

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/6518038/6522298/06522337.pdf?arnumber=6522337

Cited by 69 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Re-Cache: Mitigating cache contention by exploiting locality characteristics with reconfigurable memory hierarchy for GPGPUs;Microelectronics Journal;2023-08

2. Criticality-aware priority to accelerate GPU memory access;The Journal of Supercomputing;2022-07-06

3. Repurposing GPU Microarchitectures with Light-Weight Out-Of-Order Execution;IEEE Transactions on Parallel and Distributed Systems;2022-02-01

4. Power Prediction in Register Files Using Machine Learning;IEEE Access;2022

5. ICAP: Designing Inrush Current Aware Power Gating Switch for GPGPU;2021 IEEE International Conference on Networking, Architecture and Storage (NAS);2021-10

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