Probabilistic Evaluation of Hardware Security Vulnerabilities

Abstract

Various design techniques can be applied to implement the finite state machine (FSM) functions in order to optimize timing, performance, power, and to reduce overhead. Recently, malicious attacks to hardware systems have emerged as a critical problem. Fault injection attacks, in particular, alter the function or reveal the critical information of a hardware system through precisely controlled fault injection processes. Attackers can utilize the loopholes and vulnerabilities of FSM functions to access the states that are under protection. A probabilistic model is developed in this article to evaluate the potential vulnerabilities of FSM circuits at the design stage. Analysis based on the statistical behaviors of FSM also shows that the induced circuit errors can be exploited to access the protected states. An effective solution based on state re-encoding is proposed to minimize the risk of unauthorized transitions. Simulation results demonstrate that vulnerable transition paths can be protected with small hardware overheads.