Dark silicon as a challenge for hardware/software co-design

Author:

Shafique Muhammad1,Garg Siddharth2,Mitra Tulika3,Parameswaran Sri4,Henkel Jörg1

Affiliation:

1. Karlsruhe Institute of Technology, Germany

2. University of Waterloo, Canada

3. National University of Singapore, Singapore

4. University of New South Wales, Australia

Publisher

ACM

Reference38 articles.

1. Designing for dark silicon

2. darkNoC

3. Dynamic voltage and frequency scaling for shared resources in multicore processor designs

4. Architecture support for accelerator-rich CMPs

5. Within-die variation-aware dynamic-voltage-frequency-scaling with optimal core allocation and thread hopping for the 80-core teraflops processor. Solid-State Circuits;Dighe Saurabh;IEEE Journal of,2011

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1. An Ageing-Aware and Temperature Mapping Algorithm for Multilevel Cache Nodes;IEEE Access;2023

2. Thermal and Performance Efficient On-Chip Surface-Wave Communication for Many-Core Systems in Dark Silicon Era;ACM Journal on Emerging Technologies in Computing Systems;2022-03-22

3. Double-Layer Energy Efficient Synchronous-Asynchronous Circuit-Switched NoC;Electronics;2021-07-29

4. Dimming Hybrid Caches to Assist in Temperature Control of Chip MultiProcessors;Proceedings of the 2020 on Great Lakes Symposium on VLSI;2020-09-07

5. Area and Energy Efficient Approximate Square Rooters for Error Resilient Applications;2020 33rd International Conference on VLSI Design and 2020 19th International Conference on Embedded Systems (VLSID);2020-01

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