Dimming Hybrid Caches to Assist in Temperature Control of Chip MultiProcessors-Reference-Cited by-同舟云学术

Dimming Hybrid Caches to Assist in Temperature Control of Chip MultiProcessors

Published:2020-09-07 Issue: Volume: Page:
ISSN:
Container-title:Proceedings of the 2020 on Great Lakes Symposium on VLSI
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Author:

Joshi Chirag¹,Das Palash²,Kulkarni Ashwini¹,Kapoor Hemangee K.³

Affiliation:

1. College Of Engineering Pune, Pune, India

2. Indian Institute of Technology, Guwahati, Guwahati, India

3. Indian Institute of Technogy, Guwahati, Guwahati, India

Publisher

ACM

Link

https://dl.acm.org/doi/pdf/10.1145/3386263.3406951

Reference28 articles.

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2. Alankar V Umdekar etal 2018. Dynamic Thermal Management by Using Task Migration in Conjunction with Frequency Scaling for Chip Multiprocessors. In VLSID. IEEE. Alankar V Umdekar et al. 2018. Dynamic Thermal Management by Using Task Migration in Conjunction with Frequency Scaling for Chip Multiprocessors. In VLSID. IEEE.

3. Christian Bienia et al. 2008a. The PARSEC benchmark suite: Characterization and architectural implications. In PACT. ACM 72--81. Christian Bienia et al. 2008a. The PARSEC benchmark suite: Characterization and architectural implications. In PACT. ACM 72--81.

4. Spin-transfer torque magnetic random access memory (STT-MRAM);Dmytro Apalkov;JETC,2013

5. Performance/thermal-aware design of 3D-stacked L2 caches for CMPs;Guangyu Sun;TODAES,2012

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