Author:
Morimura Hiroki,Shigematsu Satoshi,Konaka Shinsuke
Cited by
5 articles.
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1. Comparative Analysis of Power Reduction Techniques for 6T, 8T and 9T SRAM;Proceedings of International Conference on Communication and Artificial Intelligence;2022
2. Optimum sizing of the sleep transistor in MTCMOS technology;AEU - International Journal of Electronics and Communications;2021-08
3. Design of High Performance FinFET SRAM Cell for Write Operation;Emerging Trends in Computing and Expert Technology;2019-11-07
4. A proposed SRAM cell for low power consumption during write operation;Microelectronics International;2009-01-23
5. Stand-By Power Reduction for SRAM Memories;Low-Power Processors and Systems on Chips;2005-09-20