Comparative Analysis of Power Reduction Techniques for 6T, 8T and 9T SRAM
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Publisher
Springer Nature Singapore
Link
https://link.springer.com/content/pdf/10.1007/978-981-19-0976-4_55
Reference10 articles.
1. Agrawal R, Tomar VK (2018) Analysis of cache (SRAM) memory for JGCJHCore i™ 7 processor. In: 2018 9th international conference on computing, communication and networking technologies (ICCCNT), pp 1–8. https://doi.org/10.1109/ICCCNT.2018.8494063
2. Pathak A, Sachan D, Peta H, Goswami M (2016) A modified SRAM based low power memory design. In: 2016 29th international conference on VLSI design and 2016 15th international conference on embedded systems (VLSID), pp 122–127. https://doi.org/10.1109/VLSID.2016.80
3. Kumar M, Ubhi JS (2017) Performance evaluation of 6T, 7T and 8T SRAM at 180 nm technology. In: 2017 8th international conference on computing, communication and networking technologies (ICCCNT), pp 1–6. https://doi.org/10.1109/ICCCNT.2017.8204092
4. Morimura H, Shigematsu S, Konaka S (1999) A shared-bitline SRAM cell architecture for 1-V ultra low-power word-bit configurable macrocells. In: Proceedings. 1999 international symposium on low power electronics and design (Cat. No.99TH8477), pp 12–17. https://doi.org/10.1145/313817.313829
5. Kumar A, Rabaey J, Ramchandran K (2009) SRAM supply voltage scaling: a reliability perspective. In: 2009 10th international symposium on quality electronic design, pp 782–787. https://doi.org/10.1109/ISQED.2009.4810392
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