PIMS
Author:
Affiliation:
1. Texas Tech University
2. Pacific Northwest National Laboratory
3. Tactical Computing Labs
Publisher
ACM
Link
https://dl.acm.org/doi/pdf/10.1145/3357526.3357550
Reference44 articles.
1. A scalable processing-in-memory accelerator for parallel graph processing
2. PIM-enabled instructions
3. High Performance AXI-4.0 Based Interconnect for Extensible Smart Memory Cubes
4. Kaushik Datta Shoaib Kamil Samuel Williams Leonid Oliker John Shalf and Katherine Yelick. 2009. Optimization and performance modeling of stencil computations on modern microprocessors. SIAM review 51 1 (2009) 129--159. Kaushik Datta Shoaib Kamil Samuel Williams Leonid Oliker John Shalf and Katherine Yelick. 2009. Optimization and performance modeling of stencil computations on modern microprocessors. SIAM review 51 1 (2009) 129--159.
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2. SPARTA: Spatial Acceleration for Efficient and Scalable Horizontal Diffusion Weather Stencil Computation;Proceedings of the 37th International Conference on Supercomputing;2023-06-21
3. Casper: Accelerating Stencil Computations Using Near-Cache Processing;IEEE Access;2023
4. HybriDS;Proceedings of the 34th ACM Symposium on Parallelism in Algorithms and Architectures;2022-07-11
5. TRiM: Enhancing Processor-Memory Interfaces with Scalable Tensor Reduction in Memory;MICRO-54: 54th Annual IEEE/ACM International Symposium on Microarchitecture;2021-10-17
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