APRIL

Author:

Agarwal Anant1,Lim Beng-Hong1,Kranz David1,Kubiatowicz John1

Affiliation:

1. Laboratory for Computer Science, Massachusetts Institute of Technology, Cambridge, MA

Abstract

Processors in large-scale multiprocessors must be able to tolerate large communication latencies and synchronization delays. This paper describes the architecture of a rapid-context-switching processor called APRIL with support for fine-grain threads and synchronization. APRIL achieves high single-thread performance and supports virtual dynamic threads. A commercial RISC-based implementation of APRIL and a run-time software system that can switch contexts in about 10 cycles is described. Measurements taken for several parallel applications on an APRIL simulator show that the overhead for supporting parallel tasks based on futures is reduced by a factor of two over a corresponding implementation on the Encore Multimax. The scalability of a multiprocessor based on APRIL is explored using a performance model. We show that the SPARC-based implementation of APRIL can achieve close to 80% processor utilization with as few as three resident threads per processor in a large-scale cache-based machine with an average base network latency of 55 cycles.

Publisher

Association for Computing Machinery (ACM)

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1. DESENVOLVIMENTO DE UM PROCESSADOR DE 4 BITS COM CIRCUITOS INTEGRADOS;Revista Contemporânea;2023-09-27

2. Mobius: Packet Re-processing Hardware Architecture for Rich Policy Handling on a Network Processor;Journal of Network and Systems Management;2020-10-09

3. Fairness enforcement in switch on event multithreading;ACM Transactions on Architecture and Code Optimization;2007-09

4. References;Interconnection Networks;2003

5. Symbiotic jobscheduling for a simultaneous multithreaded processor;ACM SIGARCH Computer Architecture News;2000-12

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