Improving DRAM latency with dynamic asymmetric subarray-Reference-Cited by-同舟云学术

Improving DRAM latency with dynamic asymmetric subarray

Published:2015-12-05 Issue: Volume: Page:
ISSN:
Container-title:Proceedings of the 48th International Symposium on Microarchitecture
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Author:

Lu Shih-Lien¹,Lin Ying-Chen²,Yang Chia-Lin²

Affiliation:

1. Intel Corp., Hillsboro, Oregon

2. National Taiwan University, Taipei, Taiwan ROC

Funder

Ministry of Science and Technology of Taiwan

National Taiwan University

Publisher

ACM

Link

https://dl.acm.org/doi/pdf/10.1145/2830772.2830827

Reference29 articles.

1. R. D. Williams T. Sze D. Huang S. Pannala and C. Fang "Server memory road map " 2012. http://www.jedec.org/sites/default/files/Ricki_Dee_Williams-Final_0.pdf. R. D. Williams T. Sze D. Huang S. Pannala and C. Fang "Server memory road map " 2012. http://www.jedec.org/sites/default/files/Ricki_Dee_Williams-Final_0.pdf.

2. Micron "RLDRAM 2 SIO " 2004. http://www.micron.com/-/media/documents/products/data%20sheet/dram/576mb_rldram_2_sio.pdf. Micron "RLDRAM 2 SIO " 2004. http://www.micron.com/-/media/documents/products/data%20sheet/dram/576mb_rldram_2_sio.pdf.

3. Reducing memory access latency with asymmetric DRAM bank organizations

4. Tiered-latency DRAM: A low latency and low cost DRAM architecture

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