Tiered-latency DRAM: A low latency and low cost DRAM architecture-Reference-Cited by-同舟云学术

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Tiered-latency DRAM: A low latency and low cost DRAM architecture

Published:2013-02 Issue: Volume: Page:
ISSN:
Container-title:2013 IEEE 19th International Symposium on High Performance Computer Architecture (HPCA)
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Author:

Donghyuk Lee ,Yoongu Kim ,Seshadri V.,Liu Jamie,Subramanian L.,Mutlu O.

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/6518038/6522298/06522354.pdf?arnumber=6522354

Cited by 111 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

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2. FASA-DRAM: Reducing DRAM Latency with Destructive Activation and Delayed Restoration;ACM Transactions on Architecture and Code Optimization;2024-05-21

3. Accelerating Aggregation Using a Real Processing-in-Memory System;2024 IEEE 40th International Conference on Data Engineering (ICDE);2024-05-13

4. Agile-DRAM: Agile Trade-Offs in Memory Capacity, Latency, and Energy for Data Centers;2024 IEEE International Symposium on High-Performance Computer Architecture (HPCA);2024-03-02

5. Spatial Variation-Aware Read Disturbance Defenses: Experimental Analysis of Real DRAM Chips and Implications on Future Solutions;2024 IEEE International Symposium on High-Performance Computer Architecture (HPCA);2024-03-02

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