Opportunities of Chip Power Integrity and Performance Improvement through Wafer Backside (BS) Connection-Reference-Cited by-同舟云学术

Opportunities of Chip Power Integrity and Performance Improvement through Wafer Backside (BS) Connection

Published:2022-11-03 Issue: Volume: Page:
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Container-title:Proceedings of the 24th ACM/IEEE Workshop on System Level Interconnect Pathfinding
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Author:

Chen Rongmei¹,Sisto Giuliano¹,Zografos Odysseas¹,Milojevic Dragomir¹,Weckx Pieter¹,Van der Plas Geert¹,Beyne Eric¹

Affiliation:

1. IMEC, Leuven, Belgium

Publisher

ACM

Link

https://dl.acm.org/doi/pdf/10.1145/3557988.3569716

Reference13 articles.

1. Carbon Nanotube SRAM in 5-nm Technology Node Design, Optimization, and Performance Evaluation—Part I: CNFET Transistor Optimization

2. H. Mertens , , " Forksheet FETs for Advanced CMOS Scaling: Forksheet-Nanosheet Co-Integration and Dual Work Function Metal Gates at 17nm N-P Space" 2021 Symposium on VLSI Technology , Jun. 2021 . H. Mertens, et al., "Forksheet FETs for Advanced CMOS Scaling: Forksheet-Nanosheet Co-Integration and Dual Work Function Metal Gates at 17nm N-P Space" 2021 Symposium on VLSI Technology, Jun. 2021.

3. PPAC of sheet-based CFET configurations for 4 track design with 16nm metal pitch

4. Evaluation of BEOL scaling boosters for sub-2nm using enhanced-RO analysis

5. Variability Study of MWCNT Local Interconnects Considering Defects and Contact Resistances--Part I: Pristine MWCNT

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