A gate-delay model for high-speed CMOS circuits
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ACM Press
Cited by 8 articles. 订阅此论文施引文献 订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献
1. An efficient current-based logic cell model for crosstalk delay analysis;International Journal of Electronics;2013-04
2. A Jitter Insertion and Accumulation Model for Clock Repeaters;IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences;2012
3. A Non-Iterative Method for Calculating the Effective Capacitance of CMOS Gates with Interconnect Load Effect;IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences;2011
4. Accurate Method for Calculating the Effective Capacitance with RC Loads Based on the Thevenin Model;IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences;2009
5. Waveform analysis and delay prediction for a CMOS gate driving RLC interconnect load;Integration;2007-07
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