Accurate estimation of total leakage current in scaled CMOS logic circuits based on compact current modeling-Reference-Cited by-同舟云学术

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Accurate estimation of total leakage current in scaled CMOS logic circuits based on compact current modeling

Published:2003 Issue: Volume: Page:
ISSN:
Container-title:Proceedings of the 40th conference on Design automation - DAC '03
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Author:

Mukhopadhyay Saibal,Raychowdhury Arijit,Roy Kaushik

Publisher

ACM Press

Cited by 19 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Tunneling Current Variations in Small-Sized Devices Based on a Compact Threshold Voltage Model;Applied Sciences;2023-10-17

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4. Design and Analysis of Ultra-Low Power Memory Architecture with MTCMOS Asymmetrical Ground-Gated 7T SRAM Cell;Lecture Notes in Electrical Engineering;2021

5. LEADER: Leakage Currents Estimation Technique for Aging Degradation Aware 16 nm CMOS Circuits;Communications in Computer and Information Science;2019

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