Design and Analysis of Ultra-Low Power Memory Architecture with MTCMOS Asymmetrical Ground-Gated 7T SRAM Cell
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Publisher
Springer Singapore
Link
https://link.springer.com/content/pdf/10.1007/978-981-16-1570-2_12
Reference13 articles.
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3. Wei, L., et al.: Design and optimization of dual-threshold circuits for low-voltage low-power applications. IEEE Trans. VLSI Syst. New York 7(1), 16–24 (1999)
4. Seevinck, E., List, F. J., Lohstroh, J.: Statis-noise margin analysis of MOS SRAM cells. IEEE J. Solid-State Circuits SC-22(5) (1987)
5. Sanvale, P., Gupta, N., Neema, V., Shahc, A.P., Vishvakarma, S.K.: An improved read-assist energy efficient single ended P-P-N based 10T SRAM cell for wireless sensor network. Microelectron. J. 92, 104611 (2019)
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