MetaStrider-Reference-Cited by-同舟云学术

MetaStrider

Published:2019-12-31 Issue:4 Volume:16 Page:1-26
ISSN:1544-3566
Container-title:ACM Transactions on Architecture and Code Optimization
language:en
Short-container-title:ACM Trans. Archit. Code Optim.

Author:

Srikanth Sriseshan¹^ORCID,Jain Anirudh¹,Lennon Joseph M.¹,Conte Thomas M.¹,Debenedictis Erik²,Cook Jeanine²

Affiliation:

1. Georgia Institute of Technology, Atlanta, GA

2. Sandia National Laboratories, Albuquerque, NM

Abstract

Reduction is an operation performed on the values of two or more key-value pairs that share the same key. Reduction of sparse data streams finds application in a wide variety of domains such as data and graph analytics, cybersecurity, machine learning, and HPC applications. However, these applications exhibit low locality of reference, rendering traditional architectures and data representations inefficient. This article presents MetaStrider, a significant algorithmic and architectural enhancement to the state-of-the-art, SuperStrider. Furthermore, these enhancements enable a variety of parallel, memory-centric architectures that we propose, resulting in demonstrated performance that scales near-linearly with available memory-level parallelism.

Funder

Honeywell International, Inc.

US Department of Energy's National Nuclear Security Administration

National Technology and Engineering Solutions of Sandia, LLC

Publisher

Association for Computing Machinery (ACM)

Subject

Hardware and Architecture,Information Systems,Software

Link

https://dl.acm.org/doi/pdf/10.1145/3355396

Reference79 articles.

1. Standard map reference implementation. [n.d.]. GCC std::map. Retrieved from https://gcc.gnu.org/onlinedocs/libstdc/libstdc-html-USERS-3.4/stl__map_8h-source.html. Standard map reference implementation. [n.d.]. GCC std::map. Retrieved from https://gcc.gnu.org/onlinedocs/libstdc/libstdc-html-USERS-3.4/stl__map_8h-source.html.

2. JEDEC High Bandwidth Memory Specification. [n.d.]. High bandwidth memory (HBM) DRAM. Retrieved from https://www.jedec.org/standards-documents/results/HBM. JEDEC High Bandwidth Memory Specification. [n.d.]. High bandwidth memory (HBM) DRAM. Retrieved from https://www.jedec.org/standards-documents/results/HBM.

3. Matrix Market. [n.d.]. Retrieved from https://math.nist.gov/MatrixMarket/. Matrix Market. [n.d.]. Retrieved from https://math.nist.gov/MatrixMarket/.

4. High Bandwidth Memory Characterization 1. [n.d.]. Retrieved from https://www.amd.com/Documents/High-Bandwidth-Memory-HBM.pdf. High Bandwidth Memory Characterization 1. [n.d.]. Retrieved from https://www.amd.com/Documents/High-Bandwidth-Memory-HBM.pdf.

5. High Bandwidth Memory Characterization 2. [n.d.]. Retrieved from https://www.anandtech.com/show/9969/jedec-publishes-hbm2-specification. High Bandwidth Memory Characterization 2. [n.d.]. Retrieved from https://www.anandtech.com/show/9969/jedec-publishes-hbm2-specification.

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