Tightness and computation assessment of worst-case delay bounds in wormhole networks-on-chip-Reference-Cited by-同舟云学术

Tightness and computation assessment of worst-case delay bounds in wormhole networks-on-chip

Published:2019 Issue: Volume: Page:
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Container-title:Proceedings of the 27th International Conference on Real-Time Networks and Systems - RTNS '19
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Author:

Giroudot Frederic¹,Mifdaoui Ahlem¹

Affiliation:

1. ISAE - Université de Toulouse, Toulouse, France

Publisher

ACM Press

Reference21 articles.

1. Abdallah, L., Jan, M., Ermont, J., and Fraboul, C. Wormhole networks properties and their use for optimizing worst case delay analysis of many-cores. In 10th IEEE International Symposium on Industrial Embedded Systems (SIES) (June 2015), pp. 1--10.

2. Burns, A., Indrusiak, L. S., and Shi, Z. Schedulability analysis for real time on-chip communication with wormhole switching. Int. J. Embed. Real-Time Commun. Syst. 1, 2 (Apr. 2010), 1--22.

3. Catania, V., Mineo, A., Monteleone, S., Palesi, M., and Patti, D. Cycle-accurate network on chip simulation with noxim. ACM Trans. Model. Comput. Simul. 27, 1 (Aug. 2016), 4:1--4:25.

4. Ferrandiz, T., Frances, F., and Fraboul, C. A method of computation for worst-case delay analysis on spacewire networks.

5. Giroudot, F., and Mifdaoui, A. Buffer-aware worst-case timing analysis of wormhole noes using network calculus. In 2018 IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS) (Porto, PT, 2018), pp. 1--12.

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