Buffer-Aware Worst-Case Timing Analysis of Wormhole NoCs Using Network Calculus

Author:

Giroudot Frederic,Mifdaoui Ahlem

Publisher

IEEE

Cited by 8 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. Analyzing Delay Bounds for Wormhole Network on Chip Using Network Calculus;2024

2. Poster Abstract: A Network-on-Chip Router Architecture for Industrial Internet-of-Thing Gateways;The 22nd International Conference on Information Processing in Sensor Networks;2023-05-09

3. Accurately Measuring Contention in Mesh NoCs in Time-Sensitive Embedded Systems;ACM Transactions on Design Automation of Electronic Systems;2023-04-03

4. Safety Critical Networks using Commodity SDNs;IEEE INFOCOM 2021 - IEEE Conference on Computer Communications;2021-05-10

5. Partial order based non-preemptive communication scheduling towards real-time networks-on-chip;Proceedings of the 36th Annual ACM Symposium on Applied Computing;2021-03-22

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