Integrating DRAM power-down modes in gem5 and quantifying their impact

Author:

Jagtap Radhika1,Jung Matthias2,Elsasser Wendy3,Weis Christian4,Hansson Andreas1,Wehn Norbert4

Affiliation:

1. Arm Ltd., Cambridge, U.K.

2. Fraunhofer IESE, Kaiserslautern, Germany

3. Arm Inc.

4. University of Kaiserslautern, Kaiserslautern, Germany

Funder

H2020 Future and Emerging Technologies

Fraunhofer-Gesellschaft

Deutsche Forschungsgemeinschaft

Publisher

ACM

Reference45 articles.

1. Sara Alspaugh Arka Bhattacharya David Culler and Randy Katz. 2011. The Tao of Systems: Doing Nothing Well. Sara Alspaugh Arka Bhattacharya David Culler and Randy Katz. 2011. The Tao of Systems: Doing Nothing Well.

2. Energy efficient proactive thermal management in memory subsystem

3. The gem5 simulator

4. The systems hacker's guide to the galaxy energy usage in a modern smartphone

5. Run-time power-down strategies for real-time SDRAM memory controllers

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1. OBET: On-the-Fly Byte-Level Error Tracking for Correcting and Detecting Faults in Unreliable DRAM Systems;Sensors;2021-12-10

2. Simulation of a multi-core computer system in the gem5 simulator;XLIV ACADEMIC SPACE CONFERENCE: dedicated to the memory of academician S.P. Korolev and other outstanding Russian scientists – Pioneers of space exploration;2021

3. Tackling memory access latency through DRAM row management;Proceedings of the International Symposium on Memory Systems;2018-10

4. The Role of Memories in Transprecision Computing;2018 IEEE International Symposium on Circuits and Systems (ISCAS);2018

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