Tackling memory access latency through DRAM row management-Reference-Cited by-同舟云学术

Tackling memory access latency through DRAM row management

Published:2018-10 Issue: Volume: Page:
ISSN:
Container-title:Proceedings of the International Symposium on Memory Systems
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Author:

Srikanth Sriseshan¹,Subramanian Lavanya²,Subramoney Sreenivas²,Conte Thomas M.¹,Wang Hong²

Affiliation:

1. Georgia Institute of Technology

2. Intel Labs

Publisher

ACM

Link

https://dl.acm.org/doi/pdf/10.1145/3240302.3240314

Reference38 articles.

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2. Matthew Blackmore. 2013. A quantitative analysis of memory controller page policies. (2013). Matthew Blackmore. 2013. A quantitative analysis of memory controller page policies. (2013).

3. Karthik Chandrasekar Sven Goossens Christian Weis Martijn Koedam Benny Akesson Norbert Wehn and Kees Goossens. 2014. Exploiting Expendable Process-margins in DRAMs for Run-time Performance Optimization. In DATE. Karthik Chandrasekar Sven Goossens Christian Weis Martijn Koedam Benny Akesson Norbert Wehn and Kees Goossens. 2014. Exploiting Expendable Process-margins in DRAMs for Run-time Performance Optimization. In DATE.

4. K. K. Chang P. J. Nair D. Lee S. Ghose M. K. Qureshi and O. Mutlu. 2016. Low-Cost Inter-Linked Subarrays (LISA): Enabling fast inter-subarray data movement in DRAM. In HPCA. K. K. Chang P. J. Nair D. Lee S. Ghose M. K. Qureshi and O. Mutlu. 2016. Low-Cost Inter-Linked Subarrays (LISA): Enabling fast inter-subarray data movement in DRAM. In HPCA.

5. Jungwhan Choi Wongyu Shin Jaemin Jang Jinwoong Suh Yongkee Kwon Youngsuk Moon and Lee-Sup Kim. 2015. Multiple Clone Row DRAM: A Low Latency and Area Optimized DRAM. In ISCA. 10.1145/2749469.2750402 Jungwhan Choi Wongyu Shin Jaemin Jang Jinwoong Suh Yongkee Kwon Youngsuk Moon and Lee-Sup Kim. 2015. Multiple Clone Row DRAM: A Low Latency and Area Optimized DRAM. In ISCA. 10.1145/2749469.2750402

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