GraphAttack

Author:

Manocha Aninda1ORCID,Sorensen Tyler2,Tureci Esin1,Matthews Opeoluwa1,Aragón Juan L.3ORCID,Martonosi Margaret1

Affiliation:

1. Princeton University, Princeton, NJ

2. UC Santa Cruz, Santa Cruz, CA

3. Universidad de Murcia, Murcia, Spain

Abstract

Graph structures are a natural representation of important and pervasive data. While graph applications have significant parallelism, their characteristic pointer indirect loads to neighbor data hinder scalability to large datasets on multicore systems. A scalable and efficient system must tolerate latency while leveraging data parallelism across millions of vertices. Modern Out-of-Order (OoO) cores inherently tolerate a fraction of long latencies, but become clogged when running severely memory-bound applications. Combined with large power/area footprints, this limits their parallel scaling potential and, consequently, the gains that existing software frameworks can achieve. Conversely, accelerator and memory hierarchy designs provide performant hardware specializations, but cannot support diverse application demands. To address these shortcomings, we present GraphAttack, a hardware-software data supply approach that accelerates graph applications on in-order multicore architectures. GraphAttack proposes compiler passes to (1) identify idiomatic long-latency loads and (2) slice programs along these loads into data Producer/ Consumer threads to map onto pairs of parallel cores. Each pair shares a communication queue; the Producer asynchronously issues long-latency loads, whose results are buffered in the queue and used by the Consumer. This scheme drastically increases memory-level parallelism (MLP) to mitigate latency bottlenecks. In equal-area comparisons, GraphAttack outperforms OoO cores, do-all parallelism, prefetching, and prior decoupling approaches, achieving a 2.87× speedup and 8.61× gain in energy efficiency across a range of graph applications. These improvements scale; GraphAttack achieves a 3× speedup over 64 parallel cores. Lastly, it has pragmatic design principles; it enhances in-order architectures that are gaining increasing open-source support.

Funder

DARPA

Spanish State Research Agency

Fundacion Seneca, Region de Murcia, Programa Jimenez de la Espada

Publisher

Association for Computing Machinery (ACM)

Subject

Hardware and Architecture,Information Systems,Software

Cited by 5 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. MuchiSim: A Simulation Framework for Design Exploration of Multi-Chip Manycore Systems;2024 IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS);2024-05-05

2. DECADES: A 67mm2, 1.46TOPS, 55 Giga Cache-Coherent 64-bit RISC-V Instructions per second, Heterogeneous Manycore SoC with 109 Tiles including Accelerators, Intelligent Storage, and eFPGA in 12nm FinFET;2023 IEEE Custom Integrated Circuits Conference (CICC);2023-04

3. Dalorex: A Data-Local Program Execution and Architecture for Memory-bound Applications;2023 IEEE International Symposium on High-Performance Computer Architecture (HPCA);2023-02

4. The Implications of Page Size Management on Graph Analytics;2022 IEEE International Symposium on Workload Characterization (IISWC);2022-11

5. Tiny but mighty;Proceedings of the 49th Annual International Symposium on Computer Architecture;2022-06-11

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