Retiming-based factorization for sequential logic optimization

Author:

Bommu Surendra1,O'Neill Niall2,Ciesielski Maciej3

Affiliation:

1. Synopsys, Inc., Marlboro, MA

2. Compaq, Shrewsbury, MA

3. Univ. of Massachusetts, Amherst

Abstract

Current sequential optimization techniques apply a variety of logic transformations that mainly target the combinational logic component of the circuit. Retiming is typically applied as a postprocessing step to the gate-level implementation obtained after technology mapping. This paper introduces a new sequential logic transformation which integrates retiming with logic transformations at the technology-independent level. This transformation is based on implicit retiming across logic blocks and fanout stems during logic optimization. Its application to sequential network synthesis results in the optimization of logic across register boundaries. It can be used in conjunction with any measure of circuit quality for which a fast and reliable gain estimation method can be obtained. We immplemented our new technique within the SIS framework and demonstrated its effectiveness in terms of cycle-time minimization on a set sequential benchmark circuits.

Publisher

Association for Computing Machinery (ACM)

Subject

Electrical and Electronic Engineering,Computer Graphics and Computer-Aided Design,Computer Science Applications

Reference22 articles.

1. Optimizing power using transformations

2. Synchronous logic synthesis: algorithms for cycle-time minimization

3. DE MICHELI G. 1994. Synthesis and Optimization of Digital Circuits. McGraw-Hill Inc. New York NY. DE MICHELI G. 1994. Synthesis and Optimization of Digital Circuits. McGraw-Hill Inc. New York NY.

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