How many addressing modes are enough?

Author:

Chow F.1,Correll S.1,Himelstein M.1,Killian E.1,Weber L.1

Affiliation:

1. MIPS Computer Systems, Inc., Sunnyvale, CA

Publisher

ACM

Reference6 articles.

1. VLSI Processor Architecture

2. John Moussouris , Les Crudele , Dan Freitas , Craig Hansen , Ed Hudson , Steve Przybylski , Tom Riordan , and Chris Rowen , " A CMOS RISC Processor with Integrated System Functions ," Proceedings COMPCON, IEEE, (March 4--6 , 1986 ). John Moussouris, Les Crudele, Dan Freitas, Craig Hansen, Ed Hudson, Steve Przybylski, Tom Riordan, and Chris Rowen, "A CMOS RISC Processor with Integrated System Functions," Proceedings COMPCON, IEEE, (March 4--6, 1986).

3. MIPS Computer Systems , Inc. , MIPS R2000 Processor User's Guide. 1987 . MIPS Computer Systems, Inc., MIPS R2000 Processor User's Guide. 1987.

4. Fred Chow , Mark Himelstein , Earl Killian , and Larry Weber , " Engineering a RISC Compiler System ," Proceedings COMPCON, IEEE, (March 4--6 , 1986 ). Fred Chow, Mark Himelstein, Earl Killian, and Larry Weber, "Engineering a RISC Compiler System," Proceedings COMPCON, IEEE, (March 4--6, 1986).

5. MIPS Computer Systems Inc. MIPS Language Programmer's Guide. 1986. MIPS Computer Systems Inc. MIPS Language Programmer's Guide . 1986.

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2. High-bandwidth address translation for multiple-issue processors;ACM SIGARCH Computer Architecture News;1996-05

3. Streamlining data cache access with fast address calculation;ACM SIGARCH Computer Architecture News;1995-05

4. Eliminating the address translation bottleneck for physical address cache;ACM SIGPLAN Notices;1992-09

5. Performance optimization of pipelined primary cache;ACM SIGARCH Computer Architecture News;1992-05

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