Auxiliary state machines + context-triggered properties in verification

Author:

Banerjee Ansuman1,Dasgupta Pallab1,Chakrabarti P. P.1

Affiliation:

1. Indian Institute of Technology, Kharagpur, India

Abstract

Formal specifications of interface protocols between a design-under-test and its environment mostly consist of two types of correctness requirements, namely (a) a set of invariants that applies throughout the protocol execution and (b) a set of context-triggered properties that applies only when the protocol state belongs to a specific set of contexts. To model such requirements, an increasingly popular design choice in the assertion IP design community has been the use of abstract context state machines and state-oriented properties. In this paper, we formalize this modeling style and present algorithms for verifying such specifications. Specifically, we present a purely formal approach and a semi-formal approach for verifying such specifications. We demonstrate the use of this design style in modeling some of the industry standard protocol descriptions and present encouraging results.

Publisher

Association for Computing Machinery (ACM)

Subject

Electrical and Electronic Engineering,Computer Graphics and Computer-Aided Design,Computer Science Applications

Cited by 3 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. Analysis of Machine Learning Techniques for Time Domain Waveform Prediction in Analog and Mixed Signal Integrated Circuit Verification;2023 24th International Symposium on Quality Electronic Design (ISQED);2023-04-05

2. Feature Indented Assertions for Analog and Mixed-Signal Validation;IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems;2016-11

3. Auxiliary Specifications for Context-Sensitive Monitoring of AMS Assertions;IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems;2011-10

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