Analytical Clustering Score with Application to Post-Placement Multi-Bit Flip-Flop Merging

Author:

Xu Chang1,Li Peixin1,Luo Guojie2,Shi Yiyu3,Jiang Iris Hui-Ru4

Affiliation:

1. Peking University, Beijing, China

2. PKU-UCLA Joint Research Institute in Science and Engineering, Peking University, Beijing, China

3. Missouri University of Science and Technology, Rolla, MO, USA

4. National Chiao Tung University, Hsinchu, Taiwan Roc

Funder

Research Fund for the Doctoral Program of Higher Education of China(MoE/RFDP)

Beijing Natural Science Foundation(BJNSF)

National Natural Science Foundation of China(NSFC)

Publisher

ACM

Reference21 articles.

1. Encounter rtl compiler advanced physical option datasheet 2014. http://www.cadence.com/rl/resources/datasheets/rtl_physical_ds.pdf. Encounter rtl compiler advanced physical option datasheet 2014. http://www.cadence.com/rl/resources/datasheets/rtl_physical_ds.pdf.

2. Iwls 2005 benchmarks. http://iwls.org/iwls2005/benchmarks.html. Iwls 2005 benchmarks. http://iwls.org/iwls2005/benchmarks.html.

3. A semi-persistent clustering technique for VLSI circuit placement

4. Routability-driven flip-flop merging process for clock power reduction

5. Power-aware placement

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1. Design Of Modified Data Driven Clock Gating And Look Ahead Clock Gating For Low Power;International Journal of Electrical and Electronics Research;2018-05-25

2. Minimizing detection-to-boosting latency toward low-power error-resilient circuits;Integration;2017-06

3. Improved flop tray-based design implementation for power reduction;Proceedings of the 35th International Conference on Computer-Aided Design;2016-11-07

4. Latch Clustering for Minimizing Detection-to-Boosting Latency Toward Low-Power Resilient Circuits;Proceedings of the 18th System Level Interconnect Prediction Workshop;2016-06-04

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