Author:
Cheon Yongseok,Ho Pei-Hsin,Kahng Andrew B.,Reda Sherief,Wang Qinke
Cited by
16 articles.
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2. Clock Aware Low Power Placement;2023 IEEE/ACM International Conference on Computer Aided Design (ICCAD);2023-10-28
3. Progress of Placement Optimization for Accelerating VLSI Physical Design;Electronics;2023-01-09
4. Soft-Clustering Driven Flip-flop Placement Targeting Clock-induced OCV;Proceedings of the 2020 International Symposium on Physical Design;2020-03-20
5. A fast temperature-aware fixed-outline floorplanning framework using convex optimization;Integration;2017-06