"Smart" design space sampling to predict Pareto-optimal solutions

Author:

Zuluaga Marcela1,Krause Andreas1,Milder Peter2,Püschel Markus1

Affiliation:

1. ETH Zurich

2. Carnegie Mellon University

Abstract

Many high-level synthesis tools offer degrees of freedom in mapping high-level specifications to Register-Transfer Level descriptions. These choices do not affect the functional behavior but span a design space of different cost-performance tradeoffs. In this paper we present a novel machine learning-based approach that efficiently determines the Pareto-optimal designs while only sampling and synthesizing a fraction of the design space. The approach combines three key components: (1) A regression model based on Gaussian processes to predict area and throughput based on synthesis training data. (2) A "smart" sampling strategy, GP-PUCB, to iteratively refine the model by carefully selecting the next design to synthesize to maximize progress. (3) A stopping criterion based on assessing the accuracy of the model without access to complete synthesis data. We demonstrate the effectiveness of our approach using IP generators for discrete Fourier transforms and sorting networks. However, our algorithm is not specific to this application and can be applied to a wide range of Pareto front prediction problems.

Publisher

Association for Computing Machinery (ACM)

Subject

Computer Graphics and Computer-Aided Design,Software

Cited by 12 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. Graph Neural Networks for High-Level Synthesis Design Space Exploration;ACM Transactions on Design Automation of Electronic Systems;2022-12-24

2. Q-PIR: A quantile based Pareto iterative refinement approach for high-level synthesis;Engineering Science and Technology, an International Journal;2022-10

3. N-PIR: A Neighborhood-Based Pareto Iterative Refinement Approach for High-Level Synthesis;Arabian Journal for Science and Engineering;2022-08-20

4. Learning from the Past: Efficient High-level Synthesis Design Space Exploration for FPGAs;ACM Transactions on Design Automation of Electronic Systems;2022-02-12

5. Cluster-Based Heuristic for High Level Synthesis Design Space Exploration;IEEE Transactions on Emerging Topics in Computing;2021-01-01

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