Q-PIR: A quantile based Pareto iterative refinement approach for high-level synthesis

Author:

Belwal Meena,Ramesh T.K.

Publisher

Elsevier BV

Subject

Metals and Alloys,Computer Networks and Communications,Fluid Flow and Transfer Processes,Hardware and Architecture,Mechanical Engineering,Biomaterials,Civil and Structural Engineering,Electronic, Optical and Magnetic Materials

Reference38 articles.

1. A study of memory access patterns as an indicator of performance in high-level synthesis;Belwal,2018

2. Enabling seamless execution on hybrid cpu/fpga systems: Challenges & directions;Belwal,2015

3. S.N. Daniel, D. Gajski, Frank Vahid, J. Gong, Specification and Design of Embedded Systems. Pearson Education, 2007. [Online]. Available: https://books.google.co.in/books?id=-Qn8GrsmmqYC.

4. High level synthesis for retiming stochastic vlsi signal processing architectures;Krishnapriya;Procedia Comput. Sci.,2018

5. B.T.S. Bala, K.R. Krishnanun, High level synthesis for design space exploration, ARPN J. Eng. Appl. Sci. 11 (2016) 1370–1375.

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2. A fast MILP solver for high-level synthesis based on heuristic model reduction and enhanced branch and bound algorithm;The Journal of Supercomputing;2023-03-06

3. N-PIR: A Neighborhood-Based Pareto Iterative Refinement Approach for High-Level Synthesis;Arabian Journal for Science and Engineering;2022-08-20

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