Snap-3D: A Constrained Placement-Driven Physical Design Methodology for Face-to-Face-Bonded 3D ICs-Reference-Cited by-同舟云学术

Snap-3D: A Constrained Placement-Driven Physical Design Methodology for Face-to-Face-Bonded 3D ICs

Published:2021-03-21 Issue: Volume: Page:
ISSN:
Container-title:Proceedings of the 2021 International Symposium on Physical Design
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Author:

Vanna-Iampikul Pruek¹,Shao Chengjia¹,Lu Yi-Chen¹,Pentapati Sai¹,Lim Sung Kyu¹

Affiliation:

1. Georgia Institute of Technology, Atlanta, GA, USA

Funder

This research is partially funded by the DARPA ERI 3DSOC Program

This research is partially funded by the National Research Foundation of Korea

This research is partially funded by the Semiconductor Research Corporation

Publisher

ACM

Link

https://dl.acm.org/doi/pdf/10.1145/3439706.3447049

Reference10 articles.

1. Shrunk-2-D: A Physical Design Methodology to Build Commercial- Quality Monolithic 3-D ICs;S. Panth;IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems,2017

2. Compact-2D: A Physical Design Methodology to Build Two-Tier Gate-Level 3-D ICs

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