An Implementation and Experimental Evaluation of Hardware Accelerated Ciphers in All-Programmable SoCs-Reference-Cited by-同舟云学术

An Implementation and Experimental Evaluation of Hardware Accelerated Ciphers in All-Programmable SoCs

Published:2017-04-13 Issue: Volume: Page:
ISSN:
Container-title:Proceedings of the SouthEast Conference
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Author:

Cowart R.¹,Coe D.¹,Kulick J.¹,Milenković A.¹

Affiliation:

1. Electrical and Computer Engineering, The University of Alabama in Huntsville; Huntsville, AL

Funder

National Security Agency

National Science Foundation

Publisher

ACM

Link

https://dl.acm.org/doi/pdf/10.1145/3077286.3077297

Reference17 articles.

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2. "Verilog implementation of the symmetric block cipher AES " Secworks/AES. {Online}. Available: https://github.com/secworks/aes. {Accessed: 15-Dec-2016}. "Verilog implementation of the symmetric block cipher AES " Secworks/AES. {Online}. Available: https://github.com/secworks/aes. {Accessed: 15-Dec-2016}.

3. "Xillybus: Principle of Operation " Xillybus. {Online}. Available: http://xillybus.com/doc/xilinx-pcie-principle-of-operation. {Accessed: 15-Dec-2016}. "Xillybus: Principle of Operation " Xillybus. {Online}. Available: http://xillybus.com/doc/xilinx-pcie-principle-of-operation. {Accessed: 15-Dec-2016}.

4. A 3.84 gbits/s AES crypto coprocessor with modes of operation in a 0.18-μm CMOS technology

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