1. Layout of Decoupling Capacitors in IP Blocks for 90-nm CMOS
2. Analysis and Design of On-Chip Decoupling Capacitors
3. Optimal decoupling capacitor sizing and placement for standard-cell layout designs
4. Partitioning-Based Approach to Fast On-Chip Decoupling Capacitor Budgeting and Minimization
5. M. Zhao , R. Panda , S. Sundareswaran , S. Yan , and Y. Fu , " A fast on-chip decoupling capacitance budgeting algorithm using macromodeling and linear programming," in Proc . Design Automat. Conf. , 2006 , pp. 217 -- 222 . M. Zhao, R. Panda, S. Sundareswaran, S. Yan, and Y. Fu, "A fast on-chip decoupling capacitance budgeting algorithm using macromodeling and linear programming," in Proc. Design Automat. Conf., 2006, pp. 217--222.