HPS, a new microarchitecture: rationale and introduction-Reference-Cited by-同舟云学术

HPS, a new microarchitecture: rationale and introduction

Published:1985-12 Issue:4 Volume:16 Page:103-108
ISSN:1050-916X
Container-title:ACM SIGMICRO Newsletter
language:en
Short-container-title:SIGMICRO Newsl.

Author:

Patt Y. N.¹,Hwu W. M.¹,Shebanow M.¹

Affiliation:

1. Computer Science Division, University of California, Berkeley, Berkeley, CA

Abstract

HPS (High Performance Substrate) is a new microarchitecture targeted for implementing very high performance computing engines. Our model of execution is a restriction on fine granularity data flow. This paper introduces the model, provides the rationale for its selection, and describes the data path and flow of instructions through the microengine.

Publisher

Association for Computing Machinery (ACM)

Link

https://dl.acm.org/doi/pdf/10.1145/18906.18916

Reference6 articles.

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2. Dennis J. B. and Misunas D. P. "A Preliminary Architecture for a Basic Data Flow Processor " Proceedings of the Second International Symposium on Computer Architecture 1975 pp 126-132. 10.1145/642089.642111 Dennis J. B. and Misunas D. P. "A Preliminary Architecture for a Basic Data Flow Processor " Proceedings of the Second International Symposium on Computer Architecture 1975 pp 126-132. 10.1145/642089.642111

3. Gajski D. Kuck D. Lawrie D. Sameh A. "CEDAR -- A Large Scale Multiprocessor " Computer Architecture News March 1983. 10.1145/859526.859527 Gajski D. Kuck D. Lawrie D. Sameh A. "CEDAR -- A Large Scale Multiprocessor " Computer Architecture News March 1983. 10.1145/859526.859527

4. Look-Ahead Processors

5. An Efficient Algorithm for Exploiting Multiple Arithmetic Units

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