High-Level Test Synthesis-Reference-Cited by-同舟云学术

High-Level Test Synthesis

Published:2014-08 Issue:4 Volume:19 Page:1-27
ISSN:1084-4309
Container-title:ACM Transactions on Design Automation of Electronic Systems
language:en
Short-container-title:ACM Trans. Des. Autom. Electron. Syst.

Author:

Ravi Selvaraj¹,Joseph M.²

Affiliation:

1. Sudharsan Engineering College, Pudukkottai, Tamilnadu, India

2. St. Joseph's College of Engineering and Technology, Thanjavur, Tamilnadu, India

Abstract

High-level test synthesis is a special class of high-level synthesis having testability as one of the important components. This article presents a detailed survey on recent developments in high-level test synthesis from a synthesis process flow perspective. It also presents a survey on controller synthesis techniques for testability.

Publisher

Association for Computing Machinery (ACM)

Subject

Electrical and Electronic Engineering,Computer Graphics and Computer-Aided Design,Computer Science Applications

Link

https://dl.acm.org/doi/pdf/10.1145/2627754

Reference79 articles.

1. M. Abramovici M. A. Breuer and A. D. Friedman. 2006. Digital Systems Testing and Testable Design. Jaico Publishing House India. M. Abramovici M. A. Breuer and A. D. Friedman. 2006. Digital Systems Testing and Testable Design. Jaico Publishing House India.

2. Recent directions in netlist partitioning: a survey

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