Secure Hierarchy-Aware Cache Replacement Policy (SHARP)

Author:

Yan Mengjia1,Gopireddy Bhargava1,Shull Thomas1,Torrellas Josep1

Affiliation:

1. University of Illinois at Urbana-Champaign

Abstract

In cache-based side channel attacks, a spy that shares a cache with a victim probes cache locations to extract information on the victim's access patterns. For example, in evict+reload, the spy repeatedly evicts and then reloads a probe address, checking if the victim has accessed the address in between the two operations. While there are many proposals to combat these cache attacks, they all have limitations: they either hurt performance, require programmer intervention, or can only defend against some types of attacks. This paper makes the following observation for an environment with an inclusive cache hierarchy: when the spy evicts the probe address from the shared cache, the address will also be evicted from the private cache of the victim process, creating an inclusion victim. Consequently, to disable cache attacks, this paper proposes to alter the line replacement algorithm of the shared cache, to prevent a process from creating inclusion victims in the caches of cores running other processes. By enforcing this rule, the spy cannot evict the probe address from the shared cache and, hence, cannot glimpse any information on the victim's access patterns. We call our proposal SHARP (Secure Hierarchy-Aware cache Replacement Policy). SHARP efficiently defends against all existing cross-core shared-cache attacks, needs only minimal hardware modifications, and requires no code modifications. We implement SHARP in a cycle-level full-system simulator. We show that it protects against real-world attacks, and that it introduces negligible average performance degradation.

Funder

National Science Foundation

Publisher

Association for Computing Machinery (ACM)

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1. WITHDRAWN: CSCAD: An adaptive LightGBM algorithm to detect cache side-channel attacks;Future Generation Computer Systems;2024-07

2. MetaLeak: Uncovering Side Channels in Secure Processor Architectures Exploiting Metadata;2024 ACM/IEEE 51st Annual International Symposium on Computer Architecture (ISCA);2024-06-29

3. Feasibility Analysis and Performance Optimization of the Conflict Test Algorithms for Searching Eviction Sets;Lecture Notes in Computer Science;2024

4. CacheFX: A Framework for Evaluating Cache Security;Proceedings of the ACM Asia Conference on Computer and Communications Security;2023-07-10

5. Guard Cache: Creating False Cache Hits and Misses To Mitigate Side-Channel Attacks;2023 Silicon Valley Cybersecurity Conference (SVCC);2023-05-17

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