Hybrid NOrec-Reference-Cited by-同舟云学术

Hybrid NOrec

Published:2011-03-17 Issue:3 Volume:46 Page:39-52
ISSN:0362-1340
Container-title:ACM SIGPLAN Notices
language:en
Short-container-title:SIGPLAN Not.

Author:

Dalessandro Luke¹,Carouge François²,White Sean²,Lev Yossi³,Moir Mark³,Scott Michael L.⁴,Spear Michael F.²

Affiliation:

1. University of Rochester, Rochester, PA, USA

2. Lehigh University, Bethlehem, PA, USA

3. Oracle Labs, Burlington, MA, USA

4. University of Rochester, Rochester, NY, USA

Abstract

Transactional memory (TM) is a promising synchronization mechanism for the next generation of multicore processors. Best-effort Hardware Transactional Memory (HTM) designs, such as Sun's prototype Rock processor and AMD's proposed Advanced Synchronization Facility (ASF), can efficiently execute many transactions, but abort in some cases due to various limitations. Hybrid TM systems can use a compatible software TM (STM) in such cases. We introduce a family of hybrid TMs built using the recent NOrec STM algorithm that, unlike existing hybrid approaches, provide both low overhead on hardware transactions and concurrent execution of hardware and software transactions. We evaluate implementations for Rock and ASF, exploring how the differing HTM designs affect optimization choices. Our investigation yields valuable input for designers of future best-effort HTMs.

Publisher

Association for Computing Machinery (ACM)

Subject

Computer Graphics and Computer-Aided Design,Software

Link

https://dl.acm.org/doi/pdf/10.1145/1961296.1950373

Reference43 articles.

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2. Compiler and runtime support for efficient software transactional memory

3. Advanced Micro Devices. Advanced Synchronization Facility: Proposed Architectural Specification. Publication #45432 rev. 2.1 developer.amd.com/assets/45432-ASF_Spec_2.1.pdf Mar. 2009. Advanced Micro Devices. Advanced Synchronization Facility: Proposed Architectural Specification. Publication #45432 rev. 2.1 developer.amd.com/assets/45432-ASF_Spec_2.1.pdf Mar. 2009.

4. Unbounded Transactional Memory

5. Making the fast case common and the uncommon case simple in unbounded transactional memory

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