Code-size-aware mapping for synchronous dataflow graphs on multicore systems-Reference-Cited by-同舟云学术

Code-size-aware mapping for synchronous dataflow graphs on multicore systems

Published:2017-10-15 Issue: Volume: Page:
ISSN:
Container-title:Proceedings of the 2017 International Conference on Compilers, Architectures and Synthesis for Embedded Systems Companion
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Author:

Ma Mingze¹,Sakellariou Rizos¹

Affiliation:

1. The University of Manchester, UK

Publisher

ACM

Link

https://dl.acm.org/doi/pdf/10.1145/3125501.3125514

Reference6 articles.

1. Shuvra S Bhattacharyya Praveen K Murthy and Edward A Lee. 1999. Synthesis of embedded software from synchronous dataflow specifications. J. VLSI Signal Process. (1999). Shuvra S Bhattacharyya Praveen K Murthy and Edward A Lee. 1999. Synthesis of embedded software from synchronous dataflow specifications. J. VLSI Signal Process. (1999).

2. Ming-Yung Ko Claudiu Zissulescu Sebastian Puthenpurayil Shuvra S Bhattacharyya Bart Kienhuis and Ed F Deprettere. 2007. Parameterized looped schedules for compact representation of execution sequences in DSP hardware and software implementation. IEEE Trans. Signal Process. (2007). Ming-Yung Ko Claudiu Zissulescu Sebastian Puthenpurayil Shuvra S Bhattacharyya Bart Kienhuis and Ed F Deprettere. 2007. Parameterized looped schedules for compact representation of execution sequences in DSP hardware and software implementation. IEEE Trans. Signal Process. (2007).

3. S. Stuijk M.C.W. Geilen and T. Basten. 2006. SDF3: SDF For Free. In ACSD. http://www.es.ele.tue.nl/sdf3 S. Stuijk M.C.W. Geilen and T. Basten. 2006. SDF 3 : SDF For Free. In ACSD. http://www.es.ele.tue.nl/sdf3

4. Qi Tang Twan Basten Marc Geilen Sander Stuijk and Ji-Bo Wei. 2016. Mapping of synchronous dataflow graphs on MPSoCs based on parallelism enhancement. J. Parallel and Distrib. Comput. (2016). Qi Tang Twan Basten Marc Geilen Sander Stuijk and Ji-Bo Wei. 2016. Mapping of synchronous dataflow graphs on MPSoCs based on parallelism enhancement. J. Parallel and Distrib. Comput. (2016).

5. Zhiyi Yu Kaidi You Ruijin Xiao Heng Quan Peng Ou Yan Ying Haofan Yang Ming'e Jing and Xiaoyang Zeng. 2012. An 800MHz 320mW 16-core processor with message-passing and shared-memory inter-core communication mechanisms. In ISSCC. Zhiyi Yu Kaidi You Ruijin Xiao Heng Quan Peng Ou Yan Ying Haofan Yang Ming'e Jing and Xiaoyang Zeng. 2012. An 800MHz 320mW 16-core processor with message-passing and shared-memory inter-core communication mechanisms. In ISSCC.

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1. Code-size-aware Scheduling of Synchronous Dataflow Graphs on Multicore Systems;ACM Transactions on Embedded Computing Systems;2021-05-31

2. Reducing Code Size in Scheduling Synchronous Dataflow Graphs on Multicore Systems;Proceedings of the 9th Workshop and 7th Workshop on Parallel Programming and RunTime Management Techniques for Manycore Architectures and Design Tools and Architectures for Multicore Embedded Computing Platforms - PARMA-DITAM '18;2018