Chassis

Author:

Ain Antara1,Pal Debjit1,Dasgupta Pallab1,Mukhopadhyay Siddhartha1,Mukhopadhyay Rajdeep2,Gough John2

Affiliation:

1. IIT Kharagpur

2. National Semiconductor Corp.

Abstract

Power Management Units (PMUs) are large integrated circuits consisting of many predesigned mixed-signal components. PMU integration poses a serious verification problem considering the size of the integrated circuit and the complexity of analog simulation. In this article we present an approach for automatic generation of behavioral models for PMU components from top-down skeleton models, fitted with parameter values estimated by bottom-up parameter extraction algorithms. It is shown that replacing PMU components with these autogenerated hybrid automata-based abstract behavioral models enables significant simulation speedup (> 20X on our industrial test cases) and helps in early detection of integration errors. The article also justifies the level of accuracy in our models with respect to the goal of verifying integrated PMUs. The approach presented in this work is implemented in the form of a tool suite called Chassis.

Publisher

Association for Computing Machinery (ACM)

Subject

Electrical and Electronic Engineering,Computer Graphics and Computer-Aided Design,Computer Science Applications

Cited by 5 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. ForFET: A Formal Feature Evaluation Tool for Hybrid Systems;Automated Technology for Verification and Analysis;2017

2. Feature Indented Assertions for Analog and Mixed-Signal Validation;IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems;2016-11

3. Formal Interpretation of Assertion Based Features on AMS Designs;IEEE Design & Test;2014

4. Formal Verification of Analog and Mixed Signal Designs Using SPICE Circuit Simulation Traces;Journal of Electronic Testing;2013-10

5. Post-silicon debugging of PMU integration errors using behavioral models;Integration;2013-06

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