Author:
Schlickling Marc,Pister Markus
Cited by
5 articles.
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1. Deriving Pipeline Models for Timing Analysis from High-Level HDL Processor Designs;2022 20th ACM-IEEE International Conference on Formal Methods and Models for System Design (MEMOCODE);2022-10-13
2. Work in Progress: Automatic Construction of Pipeline Datapaths from High-Level HDL Code;2022 IEEE 28th Real-Time and Embedded Technology and Applications Symposium (RTAS);2022-05
3. Static Timing Analysis – What is Special?;Semantics, Logics, and Calculi;2015-12-25
4. Computation takes time, but how much?;Communications of the ACM;2014-02
5. Sensitivity of cache replacement policies;ACM Transactions on Embedded Computing Systems;2013-03