An SLC-Like Programming Scheme for MLC Flash Memory

Author:

Ho Chien-Chung1,Chang Yu-Ming2,Chang Yuan-Hao3ORCID,Kuo Tei-Wei4

Affiliation:

1. National Chung Cheng University, Chiayi, Taiwan, R.O.C.

2. Macronix International Co., Ltd., Hsinchu, Taiwan, R.O.C.

3. Academia Sinica, Taipei, Taiwan, R.O.C.

4. National Taiwan University, Taipei, Taiwan, R.O.C.

Abstract

Although the multilevel cell (MLC) technique is widely adopted by flash-memory vendors to boost the chip density and lower the cost, it results in serious performance and reliability problems. Different from past work, a new cell programming method is proposed to not only significantly improve chip performance but also reduce the potential bit error rate. In particular, a single-level cell (SLC)-like programming scheme is proposed to better explore the threshold-voltage relationship to denote different MLC bit information, which in turn drastically provides a larger window of threshold voltage similar to that found in SLC chips. It could result in less programming iterations and simultaneously a much less reliability problem in programming flash-memory cells. In the experiments, the new programming scheme could accelerate the programming speed up to 742% and even reduce the bit error rate up to 471% for MLC pages.

Funder

Ministry of Science and Technology

Publisher

Association for Computing Machinery (ACM)

Subject

Hardware and Architecture

Cited by 2 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. Mitigating Write Amplification of Dual-mode Flash Memory;2023 20th International SoC Design Conference (ISOCC);2023-10-25

2. MNFTL;ACM Transactions on Design Automation of Electronic Systems;2020-10-12

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