Architectural Enhancements in Intel® Agilex™ FPGAs
Author:
Affiliation:
1. Intel Corporation, Toronto, ON, Canada
2. Intel Corporation, Toronto, Canada
3. Intel Corporation, San Jose, CA, USA
4. Intel Corporation, High Wycombe, United Kingdom
Publisher
ACM
Link
https://dl.acm.org/doi/pdf/10.1145/3373087.3375308
Reference17 articles.
1. M. Abadi A. Agarwal etal TensorFlow: Large-Scale Machine Learning on Heterogeneous Distributed Systems. CoRR abs/1603.04467 2016. M. Abadi A. Agarwal et al. TensorFlow: Large-Scale Machine Learning on Heterogeneous Distributed Systems. CoRR abs/1603.04467 2016.
2. A 10nm high performance and low-power CMOS technology featuring 3rd generation FinFET transistors, Self-Aligned Quad Patterning, contact over active gate and cobalt local interconnects
3. FPGA routing architecture
4. Stratix™ 10 High Performance Routable Clock Networks
5. Clock skew optimization
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