Adding Tightly-Integrated Task Scheduling Acceleration to a RISC-V Multi-core Processor-Reference-Cited by-同舟云学术

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Adding Tightly-Integrated Task Scheduling Acceleration to a RISC-V Multi-core Processor

Published:2019-10-12 Issue: Volume: Page:
ISSN:
Container-title:Proceedings of the 52nd Annual IEEE/ACM International Symposium on Microarchitecture
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Author:

Morais Lucas¹,Silva Vitor¹,Goldman Alfredo¹,Alvarez Carlos²,Bosch Jaume²,Frank Michael³,Araujo Guido⁴

Affiliation:

1. University of São Paulo

2. Barcelona Supercomputing Center

3. MagiCore Inc.

4. University of Campinas

Publisher

ACM

Link

https://dl.acm.org/doi/pdf/10.1145/3352460.3358271

Reference22 articles.

1. Chisel

2. Nexus#: A Distributed Hardware Task Manager for Task-Based Programming Models

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1. Enabling HW-Based Task Scheduling in Large Multicore Architectures;IEEE Transactions on Computers;2024-01

2. RISC-V Extension for Optimized PWM Control;2023 27th International Conference on System Theory, Control and Computing (ICSTCC);2023-10-11

3. TD-NUCA: Runtime Driven Management of NUCA Caches in Task Dataflow Programming Models;SC22: International Conference for High Performance Computing, Networking, Storage and Analysis;2022-11

4. Hybrid fuzzy-based Deep Remora Reinforcement Learning Based Task Scheduling in Heterogeneous Multicore-processor;Microprocessors and Microsystems;2022-07

5. A scalable architecture for reprioritizing ordered parallelism;Proceedings of the 49th Annual International Symposium on Computer Architecture;2022-06-11

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