Enabling HW-Based Task Scheduling in Large Multicore Architectures
Author:
Affiliation:
1. Barcelona Supercomputing Center, Barcelona, Spain
2. University of Campinas, Campinas-SP, Brazil
3. Arteris Inc., Campbell, CA, USA
4. University of São Paulo, Sao Paulo-CEP, Brazil
Funder
TEXTAROSSA
Spanish Government
Generalitat de Catalunya
Fundação de Amparo à Pesquisa do Estado de São Paulo
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Subject
Computational Theory and Mathematics,Hardware and Architecture,Theoretical Computer Science,Software
Link
http://xplorestaging.ieee.org/ielx7/12/10372122/10284544.pdf?arnumber=10284544
Reference44 articles.
1. FINGERS: exploiting fine-grained parallelism in graph mining accelerators
2. Pthreads (7): Linux manual page,2021
3. MPI: A message-passing interface standard version 4.0,2021
4. CUDA C++ Programming Guide,2023
5. Evaluating;Berlin,2003
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