Low-power 3D nano/CMOS hybrid dynamically reconfigurable architecture

Author:

Zhang Wei1,Jha Niraj K.1,Shang Li2

Affiliation:

1. Princeton University, Princeton, NJ

2. University of Colorado, Boulder, CO

Abstract

In order to continue technology scaling beyond CMOS, diverse nanoarchitectures have been proposed in recent years based on emerging nanodevices, such as nanotubes, nanowires, etc. Among them, some hybrid nano/CMOS reconfigurable architectures enjoy the advantage that they can be fabricated using photolithography. NATURE is one such architecture that we have proposed recently. It comprises CMOS reconfigurable logic and CMOS fabrication-compatible nano RAMs. It uses distributed high-density and fast nano RAMs as on-chip storage for storing multiple reconfiguration copies, enabling fine-grain cycle-by-cycle reconfiguration. It supports a highly efficient computational model, called temporal logic folding, which makes possible more than an order of magnitude improvement in logic density and area-delay product, significant power reduction, and significant design flexibility in performing area-delay trade-offs. In this article, we extend NATURE in various dimensions, evaluating various FPGA approaches in the context of today's emerging technologies. First, we explore the introduction of embedded coarse-grain modules in the fine-grain NATURE architecture and present a unified dynamically reconfigurable architecture, which can significantly enhance NATURE's computation power for data-dominated applications. Second, we explore a 3D architecture for NATURE in which the nano RAM for reconfiguration storage is on one layer and the rest of the CMOS logic on another layer. This leads to further improvements in logic density and performance. Finally, we explore the possibility of using FinFETs, an emerging double-gate CMOS technology, to implement NATURE. Since power consumption is an important consideration in the deep nanometer regime, especially for FPGAs, we present a back-gate biasing methodology for flexible threshold voltage adjustment in FinFETs to significantly reduce NATURE's power consumption. Simulation results demonstrate the efficacy of the proposed methods.

Funder

Division of Computer and Network Systems

Publisher

Association for Computing Machinery (ACM)

Subject

Electrical and Electronic Engineering,Hardware and Architecture,Software

Reference64 articles.

1. Altera. 2009. Altera. http://www.altera.com. Altera. 2009. Altera. http://www.altera.com.

2. A Low-Power Reconfigurable Logic Array Based on Double-Gate Transistors

3. High Performance Silicon Nanowire Field Effect Transistors

Cited by 9 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. Drought/wetting variations in a semiarid and sub-humid region of China;Theoretical and Applied Climatology;2020-03-18

2. Slingshot Pull-In Operation for Low-Voltage Nanoelectromechanical Memory Switches;IEEE Transactions on Electron Devices;2019-04

3. An Efficient SRAM-Based Reconfigurable Architecture for Embedded Processors;IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems;2019-03

4. A Monolithic 3D Hybrid Architecture for Energy-Efficient Computation;IEEE Transactions on Multi-Scale Computing Systems;2018-10-01

5. Pipeline Reconfigurable DSP for Dynamically Reconfigurable Architectures;Circuits, Systems, and Signal Processing;2017-01-28

同舟云学术

1.学者识别学者识别

2.学术分析学术分析

3.人才评估人才评估

"同舟云学术"是以全球学者为主线,采集、加工和组织学术论文而形成的新型学术文献查询和分析系统,可以对全球学者进行文献检索和人才价值评估。用户可以通过关注某些学科领域的顶尖人物而持续追踪该领域的学科进展和研究前沿。经过近期的数据扩容,当前同舟云学术共收录了国内外主流学术期刊6万余种,收集的期刊论文及会议论文总量共计约1.5亿篇,并以每天添加12000余篇中外论文的速度递增。我们也可以为用户提供个性化、定制化的学者数据。欢迎来电咨询!咨询电话:010-8811{复制后删除}0370

www.globalauthorid.com

TOP

Copyright © 2019-2024 北京同舟云网络信息技术有限公司
京公网安备11010802033243号  京ICP备18003416号-3