Area-optimized low-latency approximate multipliers for FPGA-based hardware accelerators-Reference-Cited by-同舟云学术

Area-optimized low-latency approximate multipliers for FPGA-based hardware accelerators

Published:2018-06-24 Issue: Volume: Page:
ISSN:
Container-title:Proceedings of the 55th Annual Design Automation Conference
language:
Short-container-title:

Author:

Ullah Salim¹,Rehman Semeen²,Prabakaran Bharath Srinivas²,Kriebel Florian²,Hanif Muhammad Abdullah²,Shafique Muhammad²,Kumar Akash¹

Affiliation:

1. Technische Universität Dresden, Germany

2. Vienna University of Technology, Austria

Publisher

ACM

Link

https://dl.acm.org/doi/pdf/10.1145/3195970.3195996

Reference21 articles.

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2. N. Brunie etal 2013. Arithmetic core generation using bit heaps. In FPL. N. Brunie et al. 2013. Arithmetic core generation using bit heaps. In FPL .

3. V. K Chippa et el. 2013. Analysis and characterization of inherent application resilience for approximate computing. In DAC. 10.1145/2463209.2488873 V. K Chippa et el. 2013. Analysis and characterization of inherent application resilience for approximate computing. In DAC . 10.1145/2463209.2488873

4. A. K. Verma etal 2008. Variable Latency Speculative Addition: A New Paradigm for Arithmetic Circuit Design. In DATE. 10.1145/1403375.1403679 A. K. Verma et al. 2008. Variable Latency Speculative Addition: A New Paradigm for Arithmetic Circuit Design. In DATE . 10.1145/1403375.1403679

5. M. Shafique etal 2015. A low latency generic accuracy configurable adder. In DAC. 10.1145/2744769.2744778 M. Shafique et al. 2015. A low latency generic accuracy configurable adder. In DAC . 10.1145/2744769.2744778

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